Design of RV32I Instruction Set Architecture

This paper presents the design and implementation of a single-cycle processor based on the RV32I instruction set architecture (ISA), supporting 30 instructions. The singlecycle architecture was chosen for its simplicity, allowing each instruction to be fetched, decoded, executed, and completed within a single clock cycle. This approach is particularly wellsuited for small-scale applications where simplicity and power efficiency are prioritized over execution speed. The design incorporates essential components such as instruction memory for storing instructions, a register file for data storage, an arithmetic logic unit (ALU) to perform arithmetic and logical operations, and data memory for data storage. Control signals are generated based on the opcode to manage data flow and ensure proper execution of instructions. The processor was developed using Verilog hardware description language (HDL). The design was synthesized targeting the Arty-S7-FPGA board as the implementation platform. The design efficiently handles basic operations such as data transfer, arithmetic calculations, and control flow. The test bench is developed in verilog and the operation of all 30 instructions is verified through simulation in the Vivado software environment. This study provides a fundamental exploration of the RISC-V architecture and lays the groundwork for future advancements in more sophisticated or pipelined processor implementations.