Enhanced I²C Architecture With Integrated CRC for Error Detection in Multi-Slave Systems

Modern embedded systems and IoT devices are based on the requirement of reliable data communication; errors may lead to system malfunctions. Therefore, in this work, a Cyclic Redundancy Check mechanism is integrated into the communication process to overcome the limitations of the standard Inter-Integrated Circuit (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}^{2} \mathrm{C}$</tex>) protocol. The improved design is based on data integrity through verification of the transmitted data between the master and multiple slave devices. It can handle the minimal error-checking capability of traditional <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}^{2} \mathrm{C}$</tex> implementations. The architecture remains fully compatible with existing <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I^{2} C$</tex> standards but adds a layer of robustness against data corruption and noise. Simulation results confirm significant improvements in error detection and reliability without considerable complexity or resource overhead. This enhancement makes the improved <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{I}^{\mathbf{2}} \mathbf{C}$</tex> protocol a perfect solution for applications that require secure, stable, and efficient communication, especially in environments where reliable data transfer is a top priority. The approach gives a practical advancement for future embedded and IoT communication systems.