Scalable UART Verification using AHP VIP for Optimal Coverage

The Universal Asynchronous Receiver Transmitter (UART) Protocol used for serial communication and data exchange between devices. In order to detect or eliminate any faults present in the design, the verification of UART is important. This paper presents the design of a UART module with both the transmitter and receiver UART and this has been implemented using System Verilog. The verification process is carried out using a UVM-based AHB Verification IP (VIP)on an Vitis FPGA. The Coverage analysis block has been included in the test bench to check whether all UART functionalities have been verified. The functional coverage of 100% is achieved through two test cases one is half-duplex and other is full-duplex communication modes by a random test.