Hybrid CMOS Low Noise Amplifier with Kapu Optimizer

This article presents the design and comprehensive analysis of a CMOS RF receiver front-end that incorporates a single-stage and optimized hybrid Low Noise Amplifier (LNA) topology for wireless applications. The design presents a basic cascode inductive source degeneration (ISD) structure alongside a hybrid cascode ISD with common-gate (CG) as a feedback linearization technique utilizing the Kapu optimizer to achieve low-noise, high gain, and improved linearity for the spectrum of the 2.4 GHz wireless systems. Simulated in 45 nm CMOS technology, the proposed hybrid CMOS LNA incorporates multi-technique innovations such as cascode, ISD, CG, and current-reuse techniques enhanced by a feedback linearization and optimization approach to enable reconfigurable applications. The proposed CMOS LNA is thoroughly evaluated using circuit simulations within the Cadence AWR Design Environment, Version 22.1, demonstrating a high power gain (S21) of 31.46 dB, excellent reverse isolation (S12) of -79.8 dB, and an extremely low Noise Figure (NF) of 0.1253 dB. Additionally, the LNA demonstrates excellent simulation input-output impedance matching for enhanced stability, with reflection coefficients of S11 = -38.98 dB and S22 = -0.033 dB, while maintaining a low power consumption of only 9.1 mW from a 1 V supply. This optimized hybrid technique creates a synergistic effect that leads to an overall improvement of 91% in linearity performance compared to the conventional ISD approach. These results highlight the appropriateness of the proposed LNA for power-efficient, high-performance wireless communication systems.