Performance Optimization of Double-Tail Dynamic Controlled Comparator at 90 nm Technology

Analog to digital conversion Units with low power consumption and fast speed have long been in demand for efficient conversion systems. With respect to this demand to increase power efficiency and speed, a double tailed dynamic controlled comparator that offers reduced delay is studied. During the meticulous study through various simulations, significant reduction in technology and sizing ratios in comparators offers less power consumption. The comparator under study [11] resimulated in 90 nm CMOS technology offers a power consumption of 3.60 µW, energy efficiency of 10.03 fJ and a delay of 68. 11 ps. Process corner and Monte Carlo simulations with a 70.29 ps delay are used to confirm the comparator's resilience.