ECRL-Based Adiabatic Logic Design for the Logic Unit of an ALU in Medical Applications Using 45 nM CMOS Technology

Consumption of power is a huge challenge in Very Large Scale Integrated (VLSI) electronics circuitry as power consumption directly affects the overall performance, especially in microprocessors, microcontrollers, and embedded products, etc. One of the main components of digital technology is ALU (Arithmetic logic unit), which does the arithmetic and logic operations. This paper explores the use of adiabatic logic to design a low-power, high-performance 32-bit ALU. In logic operations (NOT, OR XOR, NOT), positive charge recovery with complementary circuit (ECRL-CPT) is used as it consumes less power. The design was simulated using Cadence Virtuoso using Generic Process Design Kit (GPDK) 45nm CMOS (which stands for Complementary Metal-Oxide Semiconductor) technology. Utilization of adiabatic logic focusing on energy recovery is promising for the future of non-electronic VLSI circuitry, especially in terms of reducing heat dissipation and extending battery life. Choosing the right adiabatic logic family for different ALU components allows designers to achieve a stability between performance and power, giving this concept a path towards today’s modern low-power Very Large Scale Integrated (VLSI) designs. this paper is based on the design of logic unit using ECRL.