A Study on Low Power Latch Comparator with Self-Cascode Pre-Amplifier

Comparator design has advanced significantly due to raising demands. In the preamplifier stage of a traditional comparator, a self-cascode structure is included into a novel comparator architecture shown in this study. A static latch is used in place of the traditional dynamic latch to improve comparison speed. The latch is further altered in the suggested design to achieve lower delay, which makes it ideal for use in biomedical devices and high-speed systems. The circuit exhibits an energy efficiency of 29.48 fJ, delay of 54.39 ps, and a power consumption of 10.58 μW. Monte Carlo and process corner simulations were used to verify robustness