Implementation of Column Line Code ECC for Image Error Correction

Nowadays, raw remote sensing images contain a significant amount of distortions; therefore, they cannot be used directly for further image analysis. Therefore, image error correction is a process of correcting the visibility of these images. In this project, the Column Line Code (CLC) Error Correction Code (ECC) is used for the process of the image error correction. The binarisation is automatically done using an online tool, based on which the inputs for the design are generated. The CLC is coded for a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2 \times 2$</tex> matrix of data bits using Verilog HDL and verified exhaustively, for which the binarized data is given as the input for the reference, which is encoded and analyzed. Further, the error-incorporated inputs are encoded and compared in the CLC ECC decoding technique and corrected. The waveforms of these designs are verified using ModelSim, and the synthesis of the design is obtained using the Cadence Genus tool for a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4 \times 4$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2 \times 2$</tex> standard CLC ECC. Similarly, the synthesis and implementation are performed using the Xilinx Vivado Tool for the Zynq ZC702 Evaluation board for a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4 \times 4$</tex> standard CLC ECC and the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4 \times 4$</tex> CLC ECC using a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2 \times 2$</tex> standard CLC ECC, to analyze the design as per the hardware implementation using a FPGA. The <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4 \times 4$</tex> CLC ECC using <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2 \times 2$</tex> standard CLC ECC results in an enhanced design with a comparison of the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4 \times 4$</tex> standard CLC ECC as per the reports analyzed from the synthesis.

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Published
2025-03-21
DOI
https://doi.org/10.1109/icsses64899.2025.11009774
Primary Topic
Semiconductor materials and devices
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article

Implementation of Column Line Code ECC for Image Error Correction

Hemanth Prasad N, Pooja Kenchetty
Semiconductor materials and devices
article

Implementation of Column Line Code ECC for Image Error Correction

Hemanth Prasad N, Pooja Kenchetty
article en

Abstract

Nowadays, raw remote sensing images contain a significant amount of distortions; therefore, they cannot be used directly for further image analysis. Therefore, image error correction is a process of correcting the visibility of these images. In this project, the Column Line Code (CLC) Error Correction Code (ECC) is used for the process of the image error correction. The binarisation is automatically done using an online tool, based on which the inputs for the design are generated. The CLC is coded for a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2 \times 2$</tex> matrix of data bits using Verilog HDL and verified exhaustively, for which the binarized data is given as the input for the reference, which is encoded and analyzed. Further, the error-incorporated inputs are encoded and compared in the CLC ECC decoding technique and corrected. The waveforms of these designs are verified using ModelSim, and the synthesis of the design is obtained using the Cadence Genus tool for a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4 \times 4$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2 \times 2$</tex> standard CLC ECC. Similarly, the synthesis and implementation are performed using the Xilinx Vivado Tool for the Zynq ZC702 Evaluation board for a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4 \times 4$</tex> standard CLC ECC and the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4 \times 4$</tex> CLC ECC using a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2 \times 2$</tex> standard CLC ECC, to analyze the design as per the hardware implementation using a FPGA. The <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4 \times 4$</tex> CLC ECC using <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2 \times 2$</tex> standard CLC ECC results in an enhanced design with a comparison of the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4 \times 4$</tex> standard CLC ECC as per the reports analyzed from the synthesis.

Amrita Vishwa Vidyapeetham (IN)
Openalex Percentile: Top 89%
Semiconductor materials and devices
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