Design of Low Power and High Speed 1-Bit Full Subtractor Using Zipper Logic Technology

Low-power design is becoming one of the most important challenges for sophisticated, very large-scale integration (VLSI) circuits. Arithmetic circuits are vital in digital VLSI, with most using combinational logic that strongly influences quantum computing. A subtractor is a crucial component of digital circuits employed in processors. Thus, making subtractors that are fast, have low power consumption, and require a small area is of major interest. A lot of initiatives have been undertaken to boost speed and decrease power dissipation. In this work, a 1-bit full subtractor block is designed using zipper logic which meets all the requirements stated above. The design was implemented in Cadence Virtuoso using 90nm technology. The performance of the proposed design is evaluated and results are reported. It has been observed that the implemented subtractor circuit using Zipper logic had a power consumption of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.362 \mu \mathrm{W}$</tex>, a delay of 9.832 ns, and 13.39 fJ as a power delay product (PDP). The experimental results show that the proposed design is area efficient, consumes low power, and operates at high speed compared to existing models.