Power and Area-Efficient Multiplier Architectures: A Comparative Study of Array, Dadda, Booth, Wallace Tree, and Vedic Multipliers

This paper presents an efficient design and performance analysis of various 64 -bit multipliers implemented at the gate level, which are essential components in digital systems such as Digital Signal Processing (DSP) and Arithmetic Logic Units (ALUs). The study evaluates five multiplier architectures: Dadda, Array, Booth, Vedic, and Wallace Tree. These designs are implemented in Verilog and synthesized using Xilinx Vivado on an FPGA platform. The analysis focuses on key design metrics, including power consumption and resource utilization. The Dadda multiplier is optimized for minimal delay through efficient reduction stages, while the Wallace Tree multiplier employs carry-save addition to reduce latency. The Booth multiplier facilitates signed multiplication with partial product minimization, and the Vedic multiplier utilizes the Urdhva-Tiryakbhyam sutra for high-speed computations. Comparative results highlight the trade-offs among these architectures, providing insights for selecting the most suitable multiplier for low-power and resourceconstrained applications.