DFT Gasket Verification Using JTAG Protocol

Design for Testability (DFT) is essential in ASIC development, enabling thorough testing to detect manufacturing faults. By integrating additional test logic, DFT ensures chip reliability, especially in complex System-on-Chip (SoC) designs. Errors in DFT implementation can compromise accuracy, causing delays, increased costs, and reliability issues. This project establishes a structured approach to verify DFT gaskets, ensuring they perform predictably, cycle-accurately, and follow strict sequencing. Deviations from specifications can lead to chip failures, potentially costing billions. A robust, reusable verification infrastructure is built using Universal Verification Methodology (UVM) and SystemVerilog. Phase-Locked Loop (PLL) inputs are controlled via Control Status Registers (CSRs) and Test Data Registers (TDRs) in DFT gaskets across multiple IP blocks, optimizing jitter performance. Verification workflows use Exceed for server connectivity, Synopsys VCS for simulation, and Verdi for debugging-ensuring systematic DFT issue detection, improving design quality, and enhancing production efficiency.