Development and Analysis of Gate Underlap GaN Gate-All-Around FETs

Gallium Nitride (GaN)-based Gate-All-Around Field Effect Transistors (GAAFETs) with advanced Gate Stack (GS) engineering have emerged as leading candidates for nextgeneration energy-efficient electronics due to their superior material properties, including high electron mobility, wide bandgap, and excellent thermal stability. This study examines the DC performance of GaN-based GAAFETs, focusing on the integration of high-k dielectric spacers and gate underlap engineering to optimize key parameters such as On-Current, leakage current, switching speed, and subthreshold swing (SS). The incorporation of high-k spacers and gate underlap effectively suppresses short-channel effects (SCEs), improving scalability and energy efficiency. These advancements align with the IRDS 2025 2nm technology roadmap, ensuring enhanced electrostatic control for ultra-low-power, high-speed applications in IoT and 5G networks. The proposed device architecture exhibits substantial performance enhancements, making GaN-based GAAFETs highly suitable for digital and RF applications in sustainable electronics. Such innovations drive the advancement of semiconductor technology, catering to the increasing demand for energy-efficient, highperformance solutions in modern electronic systems.