A Compute-in-Memory Ascon Implementation Based on a Novel 11T SRAM Processing Macro

Over the past decade, a new paradigm of computing called Compute-In-Memory (CIM) has emerged wherein traditional memory circuits, such as static random access memories (SRAMs), can be modified to perform computations on data insitu, leading to enhanced energy efficiency and performance for many applications. At the same time, the increasing importance and ubiquity of resource-constrained edge devices has led to the need for lightweight cryptography (LWC) algorithms for security applications. The potential of CIM architectures has not previously been explored in LWC hardware implementations. In this work, we present a novel 11 transistor SRAM cell and digital CIM processing macro which implements all Boolean operations (INV/NAND/NOR/XOR) completely in-memory within a single cycle. We use our design to develop a CIM implementation of the Ascon-AEAD128 (encryption) and Ascon-Hash256 (hashing) algorithms and validate our results in 65 nm CMOS technology. Our design occupies only 3.1 kGEs, consumes <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$694 \mu W$</tex> at 250 MHz, and has a maximum frequency of 1.5 GHz. With a maximum throughput of 509 Mbs and energy efficiencies of 369 Gbit/J and 126 Gbit/J for AEAD and Hash modes, our CIM macro is competitive with state-of-the-art ASICs while remaining reprogrammable for general-purpose computation.