Design And Analysis Of High-Performance 16-Bit Hybrid Adder Using Ksa & Hca Adder With Domino Logic

High-speed and efficient arithmetic units are the core of contemporary digital systems and directly influence computation performance and power consumption. In this paper, we introduce a novel hybrid adder architecture that naturally combines the superior carry propagation property of the Kogge-Stone Adder (KSA) with the structurally symmetric design of the Han-Carlson Adder (HCA). Utilizing domino logic, the new architecture exhibits substantial power reduction and computation delay reduction, making it extremely suitable for performance-oriented applications. Extensive simulations confirm the efficacy of this hybrid architecture, with substantial speed and energy efficiency improvements over traditional adder implementations. These improvements render the new hybrid adder an ideal candidate for next-generation high-speed digital processing systems, especially for Very Large-Scale Integration (VLSI) applications where power-delay optimization is critical.