A New Methodology for Calculating the Statistical Distribution of Power Supply Noise in Chip-Package-PCB Co-Design

The consumption current of the chip flowing through the power distribution network (PDN) will generate power supply noise, leading to potential system failures. The industry commonly reduces the chip’s performance to cope with worst-case power supply noise, or modifies the PDN to ensure the chip operates normally. These measures will have a significant negative impact on the system’s performance, power, area, and cost (PPAC). To address this challenge, this paper innovatively proposes a method to accurately calculate the statistical distribution of chip power noise, thereby maximize PPAC improvement. First, the chip’s load current excitation is decomposed into a combination of multiple pulse currents using a piecewise linear method, and each current is encoded accordingly. Then, the process of calculating the statistical distribution of power supply noise is derived from the response of multiple pulse currents. By comparing the computational results with transient simulation results and measurement data, the effectiveness and robustness of the proposed method are verified. The method can be integrated into oscilloscopes to measure probability density function (PDF) of power supply noise directly.