A 1.19-pJ/b 32-Gb/s Baud-Rate Receiver Employing 2UI Integrated Pattern-Based CDR and DFE Adaptation Without Data-Level Reference

This article presents a 32-Gb/s receiver employing a baud-rate clock and data recovery (CDR) and decision feedback equalizer (DFE) adaptation. The proposed receiver utilizes an integrator that integrates analog front-end outputs for two unit intervals (UIs) from the edge of data. The 2UI integration enables the implementation of the pattern-based baud-rate CDR and DFE adaptation algorithm without relying on a data-level reference (dLev). Therefore, the proposed receiver only uses zero-crossing samplers, saving power consumption and chip area. Moreover, the proposed baud-rate CDR is less sensitive to the channel conditions compared to the conventional baud-rate CDR using the Mueller and Müller phase detector (MMPD). A prototype receiver fabricated in 40-nm CMOS technology is tested with three channels to demonstrate the performance of the CDR and DFE adaptation. As a result, the receiver achieves a bit error rate (BER) less than 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> at 32 Gb/s under 16-dB channel loss. Without the need for the dLev, the proposed receiver occupies an active area of 0.026 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 38.04 mW, achieving an energy efficiency of 1.19 pJ/b.