A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique

This letter presents a 7-bit pipelined subranging ADC that integrates a 3-bit flash ADC with a ring VCO-based quantizer. A resistor-ladder-based residue shifter (RLRS) replaces traditional residue amplifiers, efficiently shifting the residue voltage into the most linear region of the KVCO, thereby eliminating the need for post-linearity calibration. Fabricated in a 28-nm FDSOI process, the ADC occupies an area of 0.009 mm2 and achieves an SNDR of 39.26 dB and an SFDR of 48.01 dB at 2.5 GS/s, while consuming 6.5 mW of power. This results in a Walden FOM of 34.6 fJ/conversion step.

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Publication Details

Journal
IEEE Solid-State Circuits Letters
Published
2025-01-01
DOI
https://doi.org/10.1109/lssc.2025.3578546
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
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article

A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique

Jaehyouk Choi, Jeonghyun Lee, Heein Yoon, Yoonseo Cho et al.
IEEE Solid-State Circuits Letters
Analog and Mixed-Signal Circuit Design
article

A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique

Jaehyouk Choi, Jeonghyun Lee, Heein Yoon, Yoonseo Cho, Jintae Kim, Sung-Jin Kim
article en

Abstract

This letter presents a 7-bit pipelined subranging ADC that integrates a 3-bit flash ADC with a ring VCO-based quantizer. A resistor-ladder-based residue shifter (RLRS) replaces traditional residue amplifiers, efficiently shifting the residue voltage into the most linear region of the KVCO, thereby eliminating the need for post-linearity calibration. Fabricated in a 28-nm FDSOI process, the ADC occupies an area of 0.009 mm2 and achieves an SNDR of 39.26 dB and an SFDR of 48.01 dB at 2.5 GS/s, while consuming 6.5 mW of power. This results in a Walden FOM of 34.6 fJ/conversion step.

IEEE Solid-State Circuits LettersVol. 8
Ulsan College (KR), Seoul National University (KR), Samsung (South Korea) (KR), Konkuk University (KR), Ulsan National Institute of Science and Technology (KR)
Openalex Percentile: Top 88%
Analog and Mixed-Signal Circuit Design
DOISourceOpenAlex
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A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique — Jaehyouk Choi, Jeonghyun Lee, et al. · IEEE Solid-State Circuits Letters (2025) | TGRS Research Map | TGRS