A Simple and Efficient Power Processing Architecture With Series Integration of PV Array for LVDC

In this article, a simple and effective power processing architecture has been proposed, in which the series integration of solar photovoltaic (PV) array is introduced for low voltage direct current (LVDC) systems. In LVDC systems, bus bars of two or three voltage levels (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\pm$</tex-math></inline-formula> 375 and 48 V) are available. This paves the way for the formation of proposed architecture, where the parallel integration of DC-DC converter and series integration of PV array between 48 and 375 V levels become possible. This ensures that power processing through DC-DC converter is significantly reduced by a margin equivalent to 375 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$-$</tex-math></inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V_{pv}$</tex-math></inline-formula>, which increases the efficiency of the PV plant. Further, the proposed architecture offers following advantages. First, there is no compromise on maximum power point tracking, second, since only fraction of PV array’s power is processed, a converter of small size can be installed, and third, the electronic switches of converter are subject to low voltage stress because of its optimum placement. The proposed architecture is designed, analyzed, and compared with conventional architecture. Through simulation studies, the operation of proposed architecture and its high efficiency have been confirmed. Finally, the experimental prototype has been developed to verify the response of proposed architecture through practical results.