High throughput event filtering: The interpolation-based DIF algorithm hardware architecture

In recent years, there has been rapid development in the field of event vision. It manifests itself both on the technical side, as better and better event sensors are available, and on the algorithmic side, as more and more applications of this technology are proposed and scientific papers are published. However, the data stream from these sensors typically contains a significant amount of noise, which varies depending on factors such as the degree of illumination in the observed scene or the temperature of the sensor. We propose a hardware architecture of the Distance-based Interpolation with Frequency Weights(DIF) filter and implement it on an FPGA chip. To evaluate the algorithm and compare it with other solutions, we have prepared a new high-resolution event dataset, which we are also releasing to the community. Our architecture achieved a throughput of 403.39 million events per second (MEPS) for a sensor resolution of 1280 × 720 and 428.45 MEPS for a resolution of 640 × 480. The averagevalues of the Area Under the Receiver Operating Characteristic (AUROC) index ranged from 0.844 to 0.999, depending on the dataset, which is comparable to the state-of-the-art filtering solutions, but with much higher throughput and better operation over a wide range of noise levels. • This paper proposes a custom, novel event stream filtering algorithm, Distance-based Interpolation with Frequency Weights (DIF), developed using the hardware-aware design methodology. It has been designed to maximise the feasibility of FPGA computational resources, achieving the highest possible throughput while maintaining minimal resource utilisation and good filtering performance. The module was verified in hardware, in FPGA logic. The system demonstrates a throughput of 403 million events per second for a resolution of 1280 × 720, and 428 million events per second for a resolution of 640 × 480. • A dataset with a resolution of 1280 × 720 was prepared to test the effectiveness of event data filtering algorithms. It includes sequences generated with the V2E simulator and those recorded with an event camera. In addition, synthetic noise of different intensities and recorded with a real sensor was used. • The efficacy of the proposed solution was evaluated for both the prepared dataset and the DVSCLEAN dataset, using the Area Under the Receiver Operating Characteristic (AUROC) metric as a performance indicator. The average AUROC value for these datasets was determined to be approximately 0.91 and 0.98, respectively. Subsequent analysis involved a comparison of the results with those obtained for the state-of-the-art algorithms.

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Publication Details

Journal
Microprocessors and Microsystems
Published
2025-06-11
DOI
https://doi.org/10.1016/j.micpro.2025.105171
Primary Topic
Advanced Memory and Neural Computing
Type
article
Field-Weighted Citation Impact
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article

High throughput event filtering: The interpolation-based DIF algorithm hardware architecture

Tomasz Kryjak, Marcin Kowalczyk
Microprocessors and Microsystems
Advanced Memory and Neural Computing
article

High throughput event filtering: The interpolation-based DIF algorithm hardware architecture

Tomasz Kryjak, Marcin Kowalczyk
article en

Abstract

In recent years, there has been rapid development in the field of event vision. It manifests itself both on the technical side, as better and better event sensors are available, and on the algorithmic side, as more and more applications of this technology are proposed and scientific papers are published. However, the data stream from these sensors typically contains a significant amount of noise, which varies depending on factors such as the degree of illumination in the observed scene or the temperature of the sensor. We propose a hardware architecture of the Distance-based Interpolation with Frequency Weights(DIF) filter and implement it on an FPGA chip. To evaluate the algorithm and compare it with other solutions, we have prepared a new high-resolution event dataset, which we are also releasing to the community. Our architecture achieved a throughput of 403.39 million events per second (MEPS) for a sensor resolution of 1280 × 720 and 428.45 MEPS for a resolution of 640 × 480. The averagevalues of the Area Under the Receiver Operating Characteristic (AUROC) index ranged from 0.844 to 0.999, depending on the dataset, which is comparable to the state-of-the-art filtering solutions, but with much higher throughput and better operation over a wide range of noise levels. • This paper proposes a custom, novel event stream filtering algorithm, Distance-based Interpolation with Frequency Weights (DIF), developed using the hardware-aware design methodology. It has been designed to maximise the feasibility of FPGA computational resources, achieving the highest possible throughput while maintaining minimal resource utilisation and good filtering performance. The module was verified in hardware, in FPGA logic. The system demonstrates a throughput of 403 million events per second for a resolution of 1280 × 720, and 428 million events per second for a resolution of 640 × 480. • A dataset with a resolution of 1280 × 720 was prepared to test the effectiveness of event data filtering algorithms. It includes sequences generated with the V2E simulator and those recorded with an event camera. In addition, synthetic noise of different intensities and recorded with a real sensor was used. • The efficacy of the proposed solution was evaluated for both the prepared dataset and the DVSCLEAN dataset, using the Area Under the Receiver Operating Characteristic (AUROC) metric as a performance indicator. The average AUROC value for these datasets was determined to be approximately 0.91 and 0.98, respectively. Subsequent analysis involved a comparison of the results with those obtained for the state-of-the-art algorithms.

Microprocessors and MicrosystemsVol. 117
Embedded Systems (United States) (US), AGH University of Krakow (PL)
Affordable and clean energy
Openalex Percentile: Top 89%
Advanced Memory and Neural Computing
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