Comprehensive Analysis and Optimization of High-Speed Multiplication Architectures and RF Energy Harvesting Techniques for Low-Power Systems

Efficient multipliers and Radio Frequency (RF) energy harvesting circuits are important in improving the performance of low-power wireless applications and embedded systems. In this study, we explore two important areas: the enhancement of multipliers, specifically Wallace Tree and Vedic multipliers, for improving computation efficiency in digital systems, and the development of a high-performance RF energy harvesting circuit using Dickson Voltage Multipliers (DVM) designed for 915 MHz operation. The expected changes include Carry Select Adder (CSLA) in the Wallace multiplier and advanced impedance matching methods in RF energy harvesting which helps in achieving a considerable improvement in speed, power consumption, and conversion efficiency. Field Programmable Gate Arrays (FPGA) and simulation results show that the modified designs outperform traditional systems, making them appropriate for applications in the Internet of Things (IoT), wearable devices, and other low-power systems.