Investigative Analysis of Three RISC-V Microarchitectures in the Context of Computer Architecture Research

The advancement of Artificial Intelligence and the diverse application of processing units such as neural processing units (NPU), tensor processor units (TPU), etc., have raised the significance of processors with custom Instruction Set Architectures (ISA) to a higher degree. Consequently, as an open-source ISA, RISC-V has gained significant popularity over the last decade in computer architecture research within both industry and academia. In this work, a comparative study has been conducted between three microarchitectural implementations of the RISC-V architecture, namely the single-cycle, multi-cycle, and pipelined processors. All three of these processors are single-core, in-order, and able to process the integer unprivileged instructions and the multiplication instructions. The processors have been evaluated in terms of their efficiency in handling different benchmark codes, cost of implementation, and potential applications. We have used Verilog Hardware Description Language (HDL) for design and simulation. The results show that the pipelined processor was 70% faster and the multi-cycle processor was 53% slower in comparison to the single-cycle processor. The average instruction execution time of the single-cycle, multi-cycle, and the pipelined processors were found to be 750ps, 1600ps, and 455ps, respectively.