Hardware Implementation of Block Floating-Point FFT Based on Approximate Computation and Conflict-Free Access

This paper proposes a novel Fast Fourier Transform hardware architecture for natural-order multi-input multi-output processing, which is based on approximate computing and the block floating-point data format. The architecture innovatively combines the low-power characteristics of approximate multipliers with the high-precision advantages of block floating-point data formats, enabling efficient processing of 2048-point and 4096-point Fast Fourier Transform data. By employing conflict-free memory access techniques, the design optimizes data scheduling, reduces idle cycles during processing, and significantly enhances energy efficiency while maintaining computational accuracy. Experimental validation demonstrates that the processor, fabricated using a 40nm process, achieves a compact chip area of 0.42 mm². Operating at a frequency of 671.14 MHz, it delivers a throughput of 1073.82 MS/s for 4096-point FFT computations, with a power consumption of only 110.85 mW and a signal-quantization-to-noise ratio of 58.51 dB. Compared to state-of-the-art designs, this architecture achieves breakthrough improvements in throughput performance while maintaining competitive energy efficiency.