Analysis of Integrator-Differentiator Transimpedance Amplifiers: Speed and Gain Tradeoff Introduced by Parasitic Capacitances

In this paper, the frequency behavior and stability of current recording systems employing continuous-time integrator-differentiator transimpedance amplifiers (TIAs) are analyzed. The proposed comprehensive analysis provides designers helpful design rules and the ability to better predict the behavior of each individual blocks as well as the overall circuit. Moreover, it demonstrates that the overall TIA circuit suffers from stability issue introduced by parasitic capacitances which the designers may underestimate its importance. This leads to a tradeoff between the speed and gain of the TIA circuit. In addition, it is shown that using a differential-output structure improves the stability issues caused by the parasitic capacitances. The simulation and measurement results of a prototype circuit implemented in a 180-nm CMOS technology verify the effectiveness of the proposed analysis.