A Comparative Study of a 4-bit Priority Encoder with 19.96ns Propagation Delay and 126.93μW Power Dissipation Using GDI Technique

This paper builds a 4-bit priority encoder circuit based on GDI (gate diffusion input) logic to accomplish this work. Its goal is impeccable reception and digital transmission of data communication. This study thoroughly examines a priority encoder's design and performance evaluation, utilizing CMOS, transmission gate, dynamic, and Gate Diffusion input (GDI) methodologies within a 45nm technology framework by Cadence Virtuoso software. The comparative study demonstrates that satisfactory outcomes were achieved by applying GDI technology. The results indicate that implementing the GDI technique in the priority encoder design yields a slew rate of 452.99 GV/s, with a power consumption of 126.93µW and a propagation delay of 19.96 ns. This study reveals that upon finalizing the layout of the GDI-based priority encoder, which occupies a physical area of 21.113µm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, further evaluations were conducted. These evaluations encompassed Monte Carlo simulations and PVT corner analysis. In conclusion, the findings of this study contribute to a comprehensive understanding of priority encoding, which is essential for effective task scheduling and the functioning of interrupt controllers.