Leveraging FD-SOI Technology for Improved Adiabatic Logic Performance

This study has proposed a new technology, Fully Depleted Silicon on Insulator (FD-SOI), which minimizes the leakage current in MOSFET while continuing to deliver high performance. Unlike other technologies, FD-SOI does not change the basic geometry of the transistor, which makes this technology more acceptable in the tech industry. Also, Adiabatic models have been used to determine the differences in power and energy consumption on different adiabatic circuits by simulating FD-SOI and CMOS technology. In VLSI, Adiabatic is a process that reduces energy dissipation and power consumption during the switching process. An industry-standard software, Cadence Tool, has been used for the simulation process using CMOS technology on 90nm and 22nm for FD-SOI. A comparative analysis has shown between different adiabatic circuits by varying the supply voltage frequency while maintaining the constant input voltage. Propagation delays in adiabatic inverter circuits have also been showing. As the other parameters of the circuit are the same, the power and energy should be almost the same on both sides. However, at the end of this study, a major difference was observed between energy dissipation and power consumption. Almost 39% of power and energy dissipation has been lessened on ECRL than the bulk adiabatic CMOS circuit. On the other hand, 43% on 2N2N2P and on PFAL, almost 59% power consumption has been lessened than bulk CMOS. A big area difference in layout has been noticed, which is almost 75% less in FD-SOI than in CMOS. The data table at 50 MHz frequency shows that the ECR logic circuit consumes the lowest power and energy among all other families, and the 2N2N2P logic circuit is higher on this list.