Design and Optimization of Decimation Filters for Sigma-Delta ADCs

The sigma-delta converter is a very precise analog-to-digital converter (ADC) and consists of two main blocks: the modulator and the digital decimation filter. It achieves high resolution by oversampling and noise shaping, which removes the noise from the desired band. Digital decimation filters are then used to reduce the output data rate of the modulator close to the Nyquist rate and at the same time filter the high frequency noise generated by the modulator or present at the input. There are numerous papers in the literature comparing numerous topologies of sigma-delta modulators in different manufacturing technologies. However, the same is not true for decimator filters, for which there are much fewer papers describing and comparing topologies in detail for an integrated circuit implementation. Therefore, the main objective of this work is to present a guideline for the design of an optimized digital decimation filter for sigma-delta ACDs with physical synthesis results in a 65 nm CMOS process. A 3rd order sigma-delta modulator with 24 kHz bandwidth and 128 of oversampling, targeting the audio band, was chosen as inputdata for the filter. This modulator was modeled and simulated in the Matlab/Simulink environment and achieved an effectivenumber of bits (ENOB) of 17.91 bits. The optimized process target to reduce power and area of the filter while maintainingthe ENOB of this modulator at the output of the ADC.