Scan Shift Power Evaluation of ISCAS89 Benchmark Circuits

Scan testing is one of the Design for Testability (DFT) techniques that is widely being used to detect the emerging manufacturing defects in nanometer process technology. However, due to the advancement in System-on-Chip (SoC), over hundred million of logic gates have been implemented in a design resulting in high power dissipation and it has been revealed that power dissipation during scan testing could achieve three times higher than during normal operation due to the switching activity. Thus, the aim of this paper is to investigate the number of scan chains and Automatic Test Pattern Generation (ATPG) X-filling method in reducing the switching power and switching activity. In this work, 12 ISCAS89 benchmark circuits are used to run the scan test by using DFT Compiler and TetraMAX ATPG from Synopsys. Single scan chain up to 20 scan chains is implemented during scan chain insertion and 4 distinct ATPG X-filling methods—random filling, 0-filling, 1-filling and adjacent filling is applied. The switching power and switching activity for each iteration is evaluated to find the optimum number of scan chains and the best ATPG X-filling for each circuit. The simulation results show that out of 12 circuits, 5 of them exhibit preference towards single-digit number of scan chains to achieve optimal switching power performance and the decrement of switching power is ranged from 0.06% to 7.18% compared to single scan chain. Meanwhile, 7 out of 12 circuits gravitate towards 0-filling in reducing switching activity. The decrement of switching activity ranged from 4.23% to 60.63%.