SET-SAT: Evaluating the Impact of Cell Area on SET Susceptibility Across Layout of Standard Cells

Integrated circuits have become more sensitive to radiation effects with the continuous downscaling of CMOS technologies. As a consequence, device reliability has become a major bottleneck, as transistors are increasingly susceptible to various sources of noise, even slight fluctuations in charge or external environmental factors can considerably influence the behavior of the device. Therefore, accurately assessing circuit reliability is essential for developing fault-tolerant approaches, potentially enabling a robust, reliability-aware automated design flow. The main goal of this work is to analyze the influence of a Single Event Transient on different cells from a set of standard cell libraries with distinct technologies. Reports generated by SET-SAT, a tool capable of extract the susceptible area of logic gates based on their layout design, were analyzed in this study. Based on the collected data, a method was proposed to estimate susceptibility by considering the susceptible area as a proportion of the total area of the analyzed circuit. Results indicate that, in certain cases, X2 cells exhibit a lower mean susceptible area compared to X1 cells. Additionally, the same input vector of a logical function can yield a different number of sensitive nodes across the cell libraries, resulting in varying levels of susceptibility.