Performance of Omega-Gate nanowire applied to Low-Dropout Voltage Regulators: A Study Based on Experimental Data

In this work, a low-dropout voltage regulator (LDO) was designed using advanced omega-gate nanowire transistors. These transistors were modeled with an error of less than 1% through a Verilog-A hardware description based on experimental data, ensuring reliable simulation of experimental results. The model validation was carried out by extracting the main transistor curves, and only after this validation, the LDO circuits were developed. Using the gm/ID design methodology, two different design targets were explored, with transistors biased at gm/ID of 7 V⁻¹ and 8 V⁻¹, and load capacitances of 10 pF and 100 pF, respectively. The LDO specifications included a supply voltage of 1.8 V, an output voltage of 1.5 V, a load current of 100 μA, and dropout voltage of 300 mV. When comparing the two bias configurations, the LDO biased with gm/ID equal 8 V⁻¹ exhibited superior performance. This design achieved a loop voltage gain of 46.48 dB, a gain-bandwidth product (GBW) of 5.8 MHz with a 10 pF load, excellent load regulation of 36.06 V/A, and line regulation of 0.93 mV/V. Furthermore, the power supply rejection ratio (PSR) reached 50.06 dB, indicating strong immunity to input voltage ripple. These results highlight the potential of omega-gate nanowire transistors (Ω-Gate) as a viable and efficient solution for the future development of LDOs in power management circuits, particularly where low power consumption and precise voltage regulation are essential.