Hardware Architecture Design for Power-Efficient Motion Estimation over Compressed Block Data

The rapid growth in global video content con-sumption demands efficient ways to handle video data. To ad-dress this demand, energy-efficient hardware solutions for real-time video encoders are crucial. Within the various stages of video encoding, the Motion Estimation (ME) step is the most critical, yet computationally demanding due to its extensive evaluations and high memory access requirements. This paper introduces two hardware architectures to mitigate the ME memory and operative unit power dissipation: a block compres-sor unit designed to compress blocks from both the Prediction Block (PB) and Candidate Blocks (CB) from a Search Area (SA), and a configurable SAD tree architecture that leverages data reuse stemming from the block compression. The use of the block compressor achieves reductions in internal memory size and power dissipation by 75% and 73.2%, respectively, even when considering the compressor overhead. Furthermore, the configurable SAD architecture achieves up to a 23% reduction in power dissipation when subjected with real HEVC inputs.