Optimized lithographic-based nanofabrication processes for the giant piezoresistance characterization of individual silicon nanowires

In this work, we aim to fabricate strained silicon nanowires (sSiNWs) to study their electric mobility and giant piezoresistance. Through techniques compatible with the CMOS technology, individual nanowires (NWs) were fabricated from strained silicon-on-insulator (sSOI) thin films with 0.8% biaxial strain. Subsequently, the buried oxide (BOX) was removed from the SOI film, thus suspending the NWs, and the new boundary condition of its surface induces mechanical stress amplification, now uniaxial in the NW longitudinal direction. The proposal is to stress the NWs to levels higher than those employed in industry and, hence, fabricate prototypes using a single-step fabrication protocol, yet with an optimized contact resistance. Parameter optimization can further result in the fabrication of MOSFETs based on a single ultra-strained NW in gate-all-around (GAA) topology, as well as chemical and physical sensors for various technological applications.