Analyzing Hardware Trojans in FPGA-Based SoCs Using Machine Learning

The rapid advancements in design and technology have significantly improved the development and manufacturing of Integrated Circuits (ICs). However, these advancements also bring security challenges, particularly the risk of malicious modifications in the ICs internal hardware known as Hardware Trojans (HTs). Ensuring the security and confidentiality of these circuits is crucial for their reliable operation in the field. This paper presents the implementation and analysis of HTs in FPGA-based System on Chips (SoCs) using two approaches. The first approach involves embedding a Hardware Trojan within an AES Cipher logic block, connected to an embedded softcore Microblaze processor running on an FPGA. The second approach involves the insertion of a Hardware Trojan in a Custom IP core connected to an ARM9 processing unit on the FPGA. In this setup, the Xilinx Linux operating system and Python programming are used to trigger the HT via an Overlay package. Comparative analysis is conducted between these implementations, evaluating their effects on device and power utilization along with other critical characteristics. The paper highlights the security threats posed by HTs and provides insights using Machine Learning Models about HTs presence.