Evaluating Aging Effects Impact on Radiation Robustness of Combinational Gates in ASAP7 FinFet Technology

This study investigates the impact of aging degradation on the performance of standard logic cells through simulations. The results show that aging affects the high-to-low (HL) and low-to-high (LH) transition times of logic gates, with simpler gates experiencing more aging than their counterparts with more inputs. Furthermore, more complex gates exhibit greater variability in degradation, particularly in HL transitions. The analysis also reveals that considering both Bias Temperature Instability (BTI) and Single Event Transient (SET) effects is crucial for designing reliable digital circuits. The comparison of BTI with SET effects relative to the fresh state highlights the significant impact of cell degradation on the robustness of logic gates.