Analysis and Extraction of Electrically Effective Channel Length in the Subthreshold Operation of Junctionless Nanowire FETs

In this work, the electrical length of Junctionless Nanowire Transistors operating in the subthreshold condition is analyzed. This work proposes an analytical model for the lat-eral depletion towards source/drain regions, which is validated using numerical simulations. Devices with different physical characteristics operating at different temperatures were con-sidered in validation. Besides that, a method for the effective channel length extraction based on the influence of short-chan-nel effects on the subthreshold slope is also presented, validated with the simulations, and applied to experimental devices.

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Publication Details

Journal
Journal of Integrated Circuits and Systems
Published
2025-05-22
DOI
https://doi.org/10.29292/jics.v20i1.937
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
Type
article
Field-Weighted Citation Impact
0.00

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article

Analysis and Extraction of Electrically Effective Channel Length in the Subthreshold Operation of Junctionless Nanowire FETs

E. C. F. da Silva, Renan Trevisoli, Rodrigo T. Doria
Journal of Integrated Circuits and Systems
Advancements in Semiconductor Devices and Circuit Design
article

Analysis and Extraction of Electrically Effective Channel Length in the Subthreshold Operation of Junctionless Nanowire FETs

E. C. F. da Silva, Renan Trevisoli, Rodrigo T. Doria
article en

Abstract

In this work, the electrical length of Junctionless Nanowire Transistors operating in the subthreshold condition is analyzed. This work proposes an analytical model for the lat-eral depletion towards source/drain regions, which is validated using numerical simulations. Devices with different physical characteristics operating at different temperatures were con-sidered in validation. Besides that, a method for the effective channel length extraction based on the influence of short-chan-nel effects on the subthreshold slope is also presented, validated with the simulations, and applied to experimental devices.

Journal of Integrated Circuits and SystemsVol. 20(1)
Centro Universitário FEI (BR), Pontifícia Universidade Católica de São Paulo (BR)
Pontifícia Universidade Católica de São Paulo, Coordenação de Aperfeiçoamento de Pessoal de Nível Superior, Conselho Nacional de Desenvolvimento Científico e Tecnológico
Openalex Percentile: Top 89%
Advancements in Semiconductor Devices and Circuit Design
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