Reducing Warpage for Polymer-Based Embedded Silicon Fan-Out (P-eSiFO) Packaging During Thermal Process Loadings

Polymer-based embedded silicon-based fan-out (P-eSiFO) is a new packaging technique which provides a way to high-density integration of high-performance chiplets. However, integrating multiple materials with diverse physical properties in the P-eSiFO leads to substantial warpage during downstream high-temperature manufacturing processes. In this study, a thermo-mechanical model of a P-eSiFO was developed to examine the thermomechanical with varying structural parameters and material selections. Test dies having an area of 0.5 cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> was embedded in a 500 μm-thick silicon carrier following the P-eSiFO process. After careful parameters optimization chip warpage can effectively decrease by over 60%. Experimental results showed that the height difference between the embedded chip and its silicon interposer can be reduced down to 1 μm with optimized parameters after high-temperature processes. This work provides useful insights for addressing multi-material warpage concerns during thermal processes in advanced packaging.