Analysis of Clock Jitter in VCO-ADCs Under Presence of Mismatch and Blocking Signals

Analog to Digital Converters based on Voltage Controlled Oscillators are assumed very tolerant to sampling clock inaccuracies. This is due to the first-order shaping of sampling-induced errors, which appear indistinguishable from VCO phase quantization errors. A closer look to VCO-ADCs reveals that jitter errors can be problematic under different kinds of inputs and are affected by circuit impairments. This paper theoretically analyzes the behavior of pseudo differential open-loop VCO-ADCs in the presence of clock jitter and provides simulations of practical cases. In spite of being noise-shaped, the error induced by jitter is shown to depend on the input signal power. In-band noise degradation due to out-of-band signal interferers is also described. Finally, we compare open-loop and closed-loop VCO-ADCs with respect to their robustness against clock jitter.