ANALYSIS OF CLOCK NETWORK DESIGN METHODS BASED ON CLOCK MESH TOPOLOGICAL STRUCTURE

Synthesis of a clock signal synchronization system (clock network) is one of the fundamental tasks in the automated design of integrated circuits. Given the growing requirements for improving the reliability, performance and energy consumption of modern microcircuits, the traditional method of designing a Buffer tree clock network is not always able to meet these requirements, so the question of developing new methods and algorithms for designing a clock network remains open. Improving the efficiency of a clock network means reducing power consumption, increasing data processing speed, and providing reliable operation under changing operating conditions or component characteristics. An overview of alternative methods for designing a clock mesh is presented. The purpose of this study is to identify unresolved issues in existing approaches to designing clock meshes, the solution of which can contribute to increasing their efficiency compared to the traditional approach. As a result, it was found that the clock mesh method is promising in the context of decreasing the size of the technological process and tightening the requirements for resistance to variations. Open directions for increasing the efficiency of a clock mesh using the clock mesh method are identified. Based on the conducted research, it can be concluded that the tasks of developing methods for increasing performance and reducing energy consumption remain relevant. The application of a hybrid method based on clock mesh has potential in the design of integrated circuits. All the considered methods serve to find a compromise between the number of elements of the clock network, its energy consumption and time parameters for delay alignment. Thus, the article provides a brief overview of the key problems of clock network design, which can help to choose the right directions for future research.