Design and Analysis of ΔΣ Modulator Analogous Bang‐Bang Digital PLL

ABSTRACT This paper presents the analysis and design methodology of a second‐order ΔΣ modulator analogous bang‐bang digital phase‐locked loop (DSBPLL). When the bang‐bang‐based digital PLL (BB‐DPLL) cannot fully track the DCO jitter, the jitter slewing effect exacerbates the in‐band noise. The proposed DSBPLL can increase the PLL filter order without using a high‐order loop filter, thereby mitigating the in‐band noise caused by input tracking jitter. Theoretical noise analysis confirmed that the proposed DSBPLL can reduce 54.3% of the integrated jitter from 100 kHz to 100 MHz, consistent with the measurement results.