Designing SOBEL Edge Detection Using VLSI on FPGA

Edge detection is a critical operation in image processing, widely used in fields such as computer vision, robotics, medical imaging, and object recognition. The Sobel operator, known for its simplicity and effectiveness, computes the gradient of pixel intensities to identify edges within an image. Traditional software-based implementations, while functional, often struggle with real-time processing requirements. The Sobel algorithm is implemented in Verilog HDL, applying 3×3 convolution kernels to compute both horizontal and vertical gradients. These gradients are combined to produce edge magnitudes that highlight the boundaries within the image. The FPGA implementation is developed and tested using the Xilinx Vivado Design Suite. The design is simulated and verified for functional correctness, with results compared to a software-based Python implementation