Fast Implementation of Quantized Neural Network Accelerators on FPGAs for Image Classification

Quantized Neural Networks (QNNs) provide an efficient alternative to conventional deep learning models by significantly reducing computational complexity, hardware costs, and power consumption. However, implementing QNNs on FieldProgrammable Gate Arrays (FPGAs) remains challenging due to the requirements of hardware design expertise, networkspecific optimization constraints, hardware compatibility issues, and accessibility barriers. This paper introduces novel methodologies to enhance the FINN framework [1], [2] for scalable acceleration and fast implementation of QNNs on FPGAs, specifically for image classification tasks. A key contribution is the Topology-Agnostic Recursive Passing Methodology, which overcomes FINN’s network-specific transformation limitations, allowing robust optimization in diverse network architectures. Additionally, a method for integrating unsupported PyTorch operations, such as native ReLU, is presented by mapping them to MultiThreshold layers, improving model compatibility. To expand hardware support, a methodology is introduced for incorporating previously unsupported FPGA boards on FINN, demonstrated through the successful integration of the PYNQ ZU board with FINN and Vivado. The effectiveness of these enhancements is validated through benchmark evaluations on the MNIST [3] dataset, as well as real-time image classification using a live video feed processed by FPGA-accelerated QNNs on both the PYNQ ZU and Z2 boards. Finally, the entire workflow is encapsulated in an intuitive, user-friendly application that enables seamless deployment of machine learning accelerators on FPGAs, eliminating the need for expertise in hardware description languages (HDLs), FPGA programming, Vivado synthesis, or circuitry. Experimental results confirm the effectiveness of the approach, demonstrating high accuracy retention, improved inference efficiency, and improved usability, making FPGA-based QNN acceleration more accessible and scalable for a wider range of applications.

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Publication Details

Published
2025-05-02
DOI
https://doi.org/10.1109/sieds65500.2025.11021206
Citations
1
Primary Topic
CCD and CMOS Imaging Sensors
Type
article
Field-Weighted Citation Impact
0.73
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Fast Implementation of Quantized Neural Network Accelerators on FPGAs for Image Classification

Lili Yang, Xiaofang Wang, Eugene Lee, Tom Xaviour et al.
1 citations
CCD and CMOS Imaging Sensors
0.73
article

Fast Implementation of Quantized Neural Network Accelerators on FPGAs for Image Classification

Lili Yang, Xiaofang Wang, Eugene Lee, Tom Xaviour, Brandon Panuccio
article en
1 citations

Abstract

Quantized Neural Networks (QNNs) provide an efficient alternative to conventional deep learning models by significantly reducing computational complexity, hardware costs, and power consumption. However, implementing QNNs on FieldProgrammable Gate Arrays (FPGAs) remains challenging due to the requirements of hardware design expertise, networkspecific optimization constraints, hardware compatibility issues, and accessibility barriers. This paper introduces novel methodologies to enhance the FINN framework [1], [2] for scalable acceleration and fast implementation of QNNs on FPGAs, specifically for image classification tasks. A key contribution is the Topology-Agnostic Recursive Passing Methodology, which overcomes FINN’s network-specific transformation limitations, allowing robust optimization in diverse network architectures. Additionally, a method for integrating unsupported PyTorch operations, such as native ReLU, is presented by mapping them to MultiThreshold layers, improving model compatibility. To expand hardware support, a methodology is introduced for incorporating previously unsupported FPGA boards on FINN, demonstrated through the successful integration of the PYNQ ZU board with FINN and Vivado. The effectiveness of these enhancements is validated through benchmark evaluations on the MNIST [3] dataset, as well as real-time image classification using a live video feed processed by FPGA-accelerated QNNs on both the PYNQ ZU and Z2 boards. Finally, the entire workflow is encapsulated in an intuitive, user-friendly application that enables seamless deployment of machine learning accelerators on FPGAs, eliminating the need for expertise in hardware description languages (HDLs), FPGA programming, Vivado synthesis, or circuitry. Experimental results confirm the effectiveness of the approach, demonstrating high accuracy retention, improved inference efficiency, and improved usability, making FPGA-based QNN acceleration more accessible and scalable for a wider range of applications.

Villanova University (US)
Openalex Percentile: Top 27%
CCD and CMOS Imaging Sensors
0.73
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