Scaling EMIB—A Comprehensive Architecture Portfolio for Localized Interconnects

Embedded multi-die interconnect bridge (EMIB) is a significant packaging technology platform currently in high-volume production, offering high-density, and localized in-package interconnects for the heterogeneous integration (HI) of chips. We describe initial success in expanding the EMIB technology envelope along four vectors i.e., pitch and wire scaling, addition of through silicon vias (TSVs) in the bridge, demonstration of an open cavity architecture, and the integration of active bridge die. All four technology vectors result in significant improvements in the HI envelope and will lead to significantly improved HI products.

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Publication Details

Journal
IEEE Transactions on Electron Devices
Published
2025-06-06
DOI
https://doi.org/10.1109/ted.2025.3574287
Citations
2
Primary Topic
Low-power high-performance VLSI design
Type
article
Field-Weighted Citation Impact
1.46
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article

Scaling EMIB—A Comprehensive Architecture Portfolio for Localized Interconnects

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2 citations
IEEE Transactions on Electron Devices
Low-power high-performance VLSI design
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article

Scaling EMIB—A Comprehensive Architecture Portfolio for Localized Interconnects

Kaladhar Radhakrishnan, Kemal Aygün, Ravi Mahajan, Rahul Manepalli, Sujit Sharan
article en
2 citations

Abstract

Embedded multi-die interconnect bridge (EMIB) is a significant packaging technology platform currently in high-volume production, offering high-density, and localized in-package interconnects for the heterogeneous integration (HI) of chips. We describe initial success in expanding the EMIB technology envelope along four vectors i.e., pitch and wire scaling, addition of through silicon vias (TSVs) in the bridge, demonstration of an open cavity architecture, and the integration of active bridge die. All four technology vectors result in significant improvements in the HI envelope and will lead to significantly improved HI products.

IEEE Transactions on Electron DevicesVol. 72(7)
Intel (United States) (US)
Openalex Percentile: Top 17%
Low-power high-performance VLSI design
1.46
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