VLSI Architecture for Edge Detection of Leaf Images

This paper proposed a new VLSI Architecture for Sobel Edge detector for Cotton and Grape leaf images. This new VLSI Architecture is tested for leaf images using Verilog HDL and Simulated and Synthesized using Xilinx Vivado tool and results shown the low power and low area, utilized less than 0.01% of LUTs and 0.13 w of power only. The same architecture is also extended for Prewitt and Laplace Edge detectors and results shown that utility of power and area is less.