Design and Analysis of 18nm finFET based 4-bit Shift Registers Using Transitional Hybrid Logic Flip-Flop

A shift register remains a kind of sequential logic circuitry primarily employed for the storage of digital data across many digital devices to enhance the functionality of digital circuits. The present paper presents an energy-effective shift register that employs a novel flip-flop involving an implicitly conditioned crossover architecture. The suggested flip-flop exhibits excellent reliability with minimal power usage. Employing four clocked devices in conjunction with the transitional condition approach further enhances the speed. In the simulations for the suggested architecture, the Serial In-Serial Out (SISO) and Parallel In-Parallel Out (PIPO) shift registers used the least amount of power. The architecture has just 16 devices and has been simulated using 18 nm finFET technology utilizing a 0.7 V power supply. The proposed flip-flop design employs hybrid logic transistors that reduce power consumption by at least 45% when compared to previous designs across various process corners. Also, the proposed flip-flop uses less power by atleast 15% across a wide supply voltage range of 0.7V to 1V, outperforming earlier devices in this respect. The suggested flip-flop is at least 20% quicker than current FFs across all process corners. The recommended 4-bit shift registers achieve the PVT criterion. It uses less power and operates slower at the Slow-Slow (SS) process corner and vice-versa at the Fast-Fast (FF) process corner. Furthermore, when the temperature rises, power utilization increases while delay decreases.