A Fast FPGA-Based Implementation of Linear and Non-Linear Image Filters

Real-time image processing plays a crucial role in various domains, including medical imaging, surveillance, and autonomous systems, where the demand for efficient hardware acceleration is paramount. Field-Programmable Gate Arrays (FPGAs) emerge as a viable solution owing to their ability to perform parallel processing and their low-latency characteristics. This study introduces an FPGA-based implementation of both linear and non-linear image filters that are specifically optimized for real-time applications. The methodology employs a coefficient file (.coe) generation technique to facilitate efficient sum-of-product calculations and swift pixel ordering within a 3×3 window, all executed within a single clock cycle. The design, implemented on a Basys-3 FPGA using Verilog HDL and synthesized in Xilinx Vivado, achieves a processing latency of 0.04 ms at a clock frequency of 464 MHz while deliberately avoiding the utilization of FPGA DSP blocks. The paper provides a comprehensive account of the methodology to ensure reproducibility, detailing preprocessing steps, data management, and the experimental framework. The results indicate that the proposed architecture enhances computational efficiency without compromising image quality, thereby making it highly suitable for real-time applications in FPGA-based image processing.