Study on Key-factors Analysis of ELK Dielectric Stress

To reduce crosstalk and latency between chip interconnection lines, filling ELK dielectric materials between chip interconnection lines has become a common phenomenon in the semiconductor industry. However, ELK dielectric materials are susceptible to mechanical stress, leading to potential cracks. During the manufacturing process, a new thermalbudget will inevitably be introduced, and the new thermal budget will increase the thermal mismatch between different materials. The mismatch of CTE between the package substrate material and the chip material causes stress. The stress will gradually spread to the chip over time, causing the ELK crack. In this paper, the global-local simulation analysis is applied to investigate ELK dielectric stress during the cooling stage of reflow process. Impacts of different structures and materials on ELK dielectric stress are analyzed. The results indicate that UBM size, pre-solder materials, substrate core CTE, bump density, PI thickness, pilliar height have a significant impact on the local stress of ELK layer.