Optimizing Polysilicon Deposition to Reduce Bump Defects in CMOS Technology

Defects in polysilicon films critically influence the performance and yield of CMOS devices during IC manufacturing. Through our practical production experience, we identified that a substantial number of bump defects emerged on the surface of the deposited u-poly layer, which had a detrimental effect on subsequent processing, device performance, and overall product yield. In this study, we characterized the thin films and investigated the mechanisms responsible for defect formation. By optimizing pressure and gas flow rates, significant improvements can be achieved in addressing the defect-related issues.