A Study of Photoresist Residue Defect Induced by Develop Condition

As the critical size of semiconductor devices decreases below 40nm, the manufacturing processes for integrated circuits will encounter increasingly severe challenges. The complexity of these processes results in a significant reduction in tolerance for defects. During the development of the wafer with oxide substrate, we encountered a Photoresist (PR) residue defect that could not be eliminated using conventional process flows. This PR residue constitutes a critical defect that adversely affects product yield and reliability, necessitating a clear understanding of its mechanism and effective reduction strategy. Although the factory can reduce PR residue to a lower level by changing PR or optimizing the development process, the defect mechanism is unknown, and require further study. An interesting phenomenon observed during experiments revealed that variations in layout, particularly when large areas of PR are opened under the same mask transmission, lead to different PR residue defect count. Under identical development conditions and mask transmission, experiments were conducted with both centralized and dispersed openings of the PR. The results demonstrated that PR residue only happened in areas where the PR was opened in sets, while the dispersed openings remained free of residue. Based on these findings, we can anticipate PR residue defects during the early design phase of product development through careful layout planning. This early prediction, made during the GDS phase of product development, significantly conserves resources and capitalizes on valuable opportunities. The research presented in this paper establishes a foundation for reducing PR residue defects, thereby enhancing product quality and reliability.