DC and RF Characteristics of Silicon FETs on 55nm Low Power Platform

This paper presents an in-depth study of the direct current (DC) and radio frequency (RF) characteristics of silicon field-effect transistors (FETs) fabricated on a 55nm low power platform. We investigate key performance metrics, including the cut-off frequency (Ft), maximum oscillation frequency (Fmax), minimum noise figure (NFmin), and flicker noise (1/f noise) to assess the effectiveness of these devices for high-frequency applications. Our findings indicate that optimizing device design and fabrication parameters significantly enhances both Ft and Fmax, leading to improved RF performance while maintaining low power consumption. Additionally, we explore the trade-offs involved in minimizing NF, highlighting the impact of channel dimensions and doping profiles on overall device performance. The study also examines Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) and inductor designs, focusing on well implant and layout optimization. These results provide valuable insights into the challenges and opportunities in the design of silicon FETs and inductors for next-generation electronic and communication systems.