A 10.2-to-14.82-GHz Low-Phase-Noise All-Digital Phase-Locked Loop
This paper presents a subsampling bang-bang all-digital phase-locked loop (SS-BB-ADPLL) implemented in the TSMC 40nm process. The proposed PLL architecture replaces conventional time-to-digital converter (TDC) with a bang-bang phase detector (BBPD), effectively reducing circuit complexity. It also utilizes a transformer-feedback dual-core digitally controlled oscillator, which further reduces phase noise and achieves low jitter performance. The design achieves a measured root mean square (RMS) jitter of 196.8 fs in integer-N mode and 707.7 fs in fractional-N mode, while demonstrating a frequency tuning range from 10.2 GHz to 14.82 GHz.
Authors
- Zihao Li (ORCID: https://orcid.org/0000-0002-5387-4030)
- Xiaoqiang Guo (ORCID: https://orcid.org/0000-0002-9375-448X)
- Ye Hongsheng
- Haoshen Zhu (ORCID: https://orcid.org/0000-0001-7972-4789)
- Wenquan Che (ORCID: https://orcid.org/0000-0002-9388-6570)
- Pei Qin (ORCID: https://orcid.org/0000-0002-1743-2200)
- Kaiming Zhong
- Quan Xue (ORCID: https://orcid.org/0000-0002-4226-2127)
- Xiang Yi (ORCID: https://orcid.org/0000-0002-0330-737X)
Institutions
- South China University of Technology (CN)
Publication Details
- Published
- 2025-03-24
- DOI
- https://doi.org/10.1109/cstic64481.2025.11017799
- Primary Topic
- Advancements in PLL and VCO Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Natural Science Foundation of China
- Fundamental Research Funds for the Central Universities