Investigation of the GIDL Current Shift Phenomenon in Symmetrical High-Voltage NMOS Devices on 55 nm Technology

A comprehensive investigation into the Gate-Induced Drain Leakage (GIDL) current shift phenomenon observed in symmetrical high-voltage (HV) NMOS devices fabricated using advanced 55nm technology was presented in this work. Through a combination of experimental measurements, device simulations, and physical analysis, we elucidate that the factors leading to the variation in leakage current are oxide traps located at the gate poly edge. The GIDL current shift phenomenon results in an unstable leakage current of HV NMOS devices, failing to meet the required specifications. In addition, this paper presents a viable solution that can effectively reduce the variation in GIDL current. The findings provide crucial insights for optimizing device design and improving reliability in future high-voltage applications.